1. Field of the Invention
This invention relates to integrated biasing circuits and more particularly to an integrated current mirror circuit having a base current error cancellation circuit.
2. Description of the Prior Art
In the past, various biasing circuits have been designed to provide a bias current source which is suitable for integration. One such type of integrated biasing circuit has come to be known as a current mirror which when used as a current source can provide current relatively independent of transistor parameters. FIG. 1 illustrates what has come to be well known in the prior art as a basic current mirror circuit. Assuming that the transistors Q1 and Q2 are identical, operate in the active region and have the same base-emitter voltage, they must also have approximately equal collector currents. In this circuit, the bias current I is determined by the following equation: EQU I=(V.sub.CC -V.sub.D)/R (1)
Then applying Kirchhoff's current law to the base node, the following relationship holds true: EQU I=I.sub.C +2I.sub.B ( 2)
Further it is well known that: EQU I.sub.C =.beta.I.sub.B ( 3)
Thus, if equations (1), (2) and (3) are combined the following relationship is obtained wherein: EQU I.sub.C =I.beta./(.beta.+2)=.beta.(V.sub.CC -V.sub.D)/(R(.beta.+2)); (4)
where the resultant error in output current is represented by the factor .beta./(.beta.+2). PA1 where the resultant error in output current is represented by the factor .beta.(.beta.+1)/(.beta.(.beta.+1)+2).
Therefore in cases where beta is in the order of 50 or larger, I.sub.C is approximately equal to I.
Such a circuit is suitable for integration because it contains no capacitors and only one resistor. However, it can be seen that when beta becomes less than 50 the base current error (i.e. the reduction in input (collector) current I.sub.C due to the loading effect of the bases of the current mirror transistors Q.sub.1 and Q.sub.2) will continue to increase, making the circuit unsuitable for cases where low beta transistors are contemplated.
As mentioned above it is well known that if beta is not large or if the number of series connected transistors in the current mirror circuit is increased, the current becomes more influenced by variations of beta. This is particularly a problem with lateral PNP transistors which inherently have low values of beta. This can also be a problem with NPN transistors where precise balance of two currents is required.
In order to overcome the aforesaid problem an improved current mirror circuit was developed which adds a new transistor Q4 in the feedback path of the circuit of FIG. 1, as shown in FIG. 2 in order to make the current less dependent on beta. In the circuit of FIG. 2: EQU I=I.sub.C +2I.sub.B /.beta.+1 (5)
Since I.sub.C equals .beta.I.sub.B then: EQU I.sub.C =I.beta.(.beta.+1)/(.beta.(.beta.+1)+2); (6)
Thus, even for moderate values of beta, I.sub.C and I will be well balanced. However, for very low values of beta, the base current error may still be too high for certain desired applications.
Another application of a current mirror circuit is illustrated in the publication "A Highly Stable VCO for Application in Monolithic Phase-Locked Loops" found in Volume SC-10, No. 6 of the IEEE Journal of Solid State Circuits, published in December of 1975 and authored by Robert R. Cordell and William G. Garrett. In FIG. 3 of that reference (not shown) found on page 482, a schematic of a VCO is illustrated in which certain circuit elements have been included to minimize the errors due to transistor base current. These elements include a Darlington connection (Q.sub.41, Q.sub.42,), current mirror "helpers" (Q.sub.43, Q.sub.49), and base bias current compensation (Q.sub.48). In this circuit the base current of helper transistor Q.sub.43 reduces the timing current delivered to the collector of Q.sub.50. Since the collector current of Q.sub.48 is essentially the same as that of Q.sub.43, its base current cancels most of the error due to the base current of Q.sub.43.
The present invention distinguishes over the prior art by providing a current mirror circuit having a base current error cancellation circuit in which the base current error is reduced by a factor of beta plus one (.beta.+1).